Semiconductors are widely used in integrated circuits for electronic applications, including various information systems. Such integrated circuits typically use multiple bipolar junction transistors (BJT) and/or metal-oxide semiconductor field-effect transistors (MOSFET) fabricated in single crystal silicon. Many integrated circuits now require the introduction of dopants to one or more device junction layers for formation of the transistor device structures. Usually when dopants are introduced into a semiconductor wafer surface, they are introduced by a process called ion implantation, wherein the substrate is bombarded by ions of a certain species, thus introducing the dopant.
A significant requirement in sub-half-micrometer, high-performance semiconductor technologies is junction depth reduction (e.g., CMOS source/drain, bipolar emitter, and base) to suppress MOS punch-through leakage and to minimize device short-channel effects. Device junctions with relatively high surface dopant concentrations, ultra-shallow depths (below 1000 .ANG.), low contact and sheet resistances, and low junction leakage currents will be critical for advanced sub-quarter-micrometer semiconductor technologies.
One problem with the ion implantation process is that the semiconductor crystal structure is damaged and later, a high temperature thermal anneal process must be performed in order to remove the defects. Another problem is that there is a limit on the shallowness of the doped junctions. In order to achieve junctions with depths on the order of 1000 .ANG. or less, alternative device doping methods must be utilized.
Alternative methods of doping include direct gas-phase doping (GPD) such as rapid thermal gas-phase doping (RTGPD) and plasma immersion ion implantation (PIII), which allow the formation of ultra-shallow junctions without the use of conventional ion implantation. Prior art GPD processes usually have employed an ambient consisting of diborane mixed with hydrogen (B.sub.2 H.sub.6 /H.sub.2) for p-type doping, to form ultra-shallow boron junctions; or phosphine mixed with hydrogen (PH.sub.3 /H.sub.2) for n-type doping, to form ultra-shallow phosphorus doped junctions. Moreover, both arsine (AsH.sub.3) and tertiarybutylarsine (TBA) have been used in GPD processes to form shallow arsenic-doped junctions. The GPD processes rely on the chemisorption of the dopant species followed by thermally activated surface dissociation of the dopant species and solid-state diffusion to form the doped junction. The GPD process usually consists of a native oxide removal process step prior to the formation of an adsorbed dopant layer on the silicon surface and subsequent solid-phase diffusion of dopants from the adsorbed layer into the silicon substrate. Dopants are incorporated into silicon by diffusion in an oxygen-free atmosphere at a relatively low temperature unlike the conventional diffusion process in which dopant diffusion is performed in an oxygen-rich ambient.
The GPD process involves species such as hydrogen, phosphine, diborane, or arsine. The dopant molecules are adsorbed on the semiconductor surface. After surface adsorption, dissociation occurs; the chemical bonds between hydrogen and the dopant atoms break, reducing the adsorbed molecules into arsenic, phosphorous, or boron atoms, which diffuse into the silicon substrate. The byproducts, e.g. hydrogen, then desorb from the surface to make the surface sites available for chemical adsorption of more dopant species.
Reduced junction depths are required in scaled-down semiconductor technologies. For instance, the source/drain junction depth must be reduced with each new IC technology generation. In general, the need for reduced junction depth is driven by the device scale-down and improved device performance. Conventional doping methods have shortcomings: the ion implantation processes and current GPD processes have limitations in terms of minimum junction depth and junction quality.
Ion implantation technology has been widely used in semiconductor device manufacturing because of its superior controllability and relatively high manufacturing throughput, but it is inadequate for junctions shallower than 1000 .ANG. because of ion channeling at low ion energies, end-of-range implant damage, lateral dopant spreading, and poor throughput and process control at low implant energies (e.g. below 10 keV). Another limitation of the implantation-formed junctions is the so-called anomalous transient-enhanced boron diffusion during low-temperature thermal annealing caused by the thermal dissolution of small defect clusters produced by ion implantation. Moreover, ion implantation is not suitable for uniform doping of high-aspect-ratio trenches. Effective removal of the implantation-induced defects in Si requires relatively high thermal annealing temperatures, which further redistribute the dopant.
The GPD processes to date have been exclusively based on the B.sub.2 H.sub.6 /H.sub.2 (for p type), PH.sub.3 /H.sub.2 (for n type), and AsH.sub.3 /H.sub.2 (for n type) chemistries. These processes do not produce any damage in silicon and are the most effective when the semiconductor surface is treated using an in-situ clean to remove any native oxide layer.